Simulation-based fault-tolerant multiprocessors system

System reliability is an important issue in designing modern multiprocessor systems. This paper proposes a fault-tolerant, scalable, system architecture that adopts pipeline scheme. To verify the performance of proposed system, SimEvent/Stateflow tool MATLAB program was used to simulate system. The uses twelve processors (P), connected linear array, build ten-stage with two backup (BP). However, can be expanded by adding more increase stages and performance, reliability. automatically reorganize itself event failure one or execution continues without interruption. Each processor communicates its neighboring through input/output (I/O) ports which are as bypass links between processors. In failure, function faulty assigned next free from faults. fast Fourier transform (FFT) algorithm implemented on simulated circuit evaluate results showed continue execute even if fail noticeable decrease performance.